1) Field of the Invention
The present invention relates to a method and apparatus used in a layout design for a routing pattern, a cell and the like on an LSI or a printed circuit board. More specifically, the present invention relates to a clock routing design method for designing a routing of clock signal lines using a hierarchical layout design.
2) Description of the Related Art
In an layout design for an LSI or a printed circuit board, it is, in general, desirable that clock signal lines routed between one driver terminal providing a clock signal and a plurality of receiver terminals receiving the clock signal are so routed that the clock signal supplied from the driver terminal reaches each of the receiver terminals substantially at the same time (exactly at the same time, ideally). A variation in a time period required until the clock signal reaches each of the receiver terminals from the driver terminal is referred as clock skew.
In recent years, there is an increasing demand for a zero skew routing of a clock signal, in other words, a routing which can provide the clock skew at zero with an increase in clock frequency in LSIs or the like. With an increase of a degree of integration of LSIs or the like, there is also an increase of demand for shortening a time period required for the layout design. To meet these two demands, it is necessary to shorten a time period required for the layout design besides realizing a minimum skew of the clock signal lines in the hierarchical layout design.
In the hierarchical layout design method, an area that is an object of the routing design on a chip is divided into a plurality of layout hierarchies. The routing inside each of the hierarchies is designed, thereafter the routing between the layout hierarchies is performed to complete the routing design overall the chip. If a degree of integration of LSIs is increased, such hierarchical layout design method allows a large decrease in a time period required for layout design as compared with a method in which the routing design of the overall chip is performed at the same time.
Now referring to FIGS. 28 through 31, a procedure of a general routing design for clock signals employing the hierarchical layout design will be described.
In FIGS. 28 through 31, an area enclosed by a thick line "Layout 0" designates an area of a chip level (the whole of a chip that is an object of the routing), and areas enclosed by thin lines "Layout 1" through "Layout 5" designate the layout hierarchies divided and set, respectively, inside the area "Layout 0" on the chip. Here is shown an example where five layout hierarchies are set.
In FIGS. 28 through 31, ".circle-solid." designates a driver terminal DV1 providing a clock signal, ".smallcircle." designates receiver terminals RV1 through RV4 receiving the clock signal supplied from the driver terminal DV1, and ".circleincircle." designates clock supplying terminals M0 through M4 set on boundaries of the respective layout hierarchies "Layout 1" through "Layout 5".
FIGS. 28 through 31 show an example where one driver terminal DV1 is disposed within the layout hierarchy "Layout 1" and the receiver terminals RV1, RV4, RV2 and RV3 are disposed in the layout hierarchies "Layout 2" through "Layout 5", respectively.
As shown in FIG. 28, the whole area "Layout 0" on the chip is divided into, for example, five areas "Layout 1" through "Layout 5" so as to hierarchize the whole chip. Thereafter, as shown in FIG. 29, positions to dispose the clock supplying terminals M0 through M4 therein are decided on boundaries of the respective layout hierarchies "Layout 1" through "Layout 5".
One clock supplying terminal is set to one layout hierarchy. In the example shown in FIG. 29, the clock supplying terminal MO used to output the clock signal supplied from the driver terminal DV1 outside the layout hierarchy "Layout 1" is set on the boundary of the layout hierarchy "Layout 1", while the clock supplying terminals M1, M4, M2 and M3 used to supply the clock signal to the receiver terminals RV1, RV4, RV2 and RV3, respectively, are set on the boundaries of the respective layout hierarchies "Layout 2" through "Layout 5".
As shown in FIG. 30, at first, a process to route the clock signal line inside each of the layout hierarchies "Layout 1" through "Layout 5" is performed, in other words, routing designs between the driver terminal DV1 and the clock supplying terminal M0, and between the receiver terminals RV1 through RV4 and the respective clock supplying terminals M1 through M4, are worked out. After that, a routing design for mutually connecting the clock supplying terminals M0 through M4 set on the boundaries of the respective layout hierarchies "Layout 1" through "Layout 5" is performed finally, as shown in FIG. 31.
As stated above, electrical connection among the layout hierarchies is performed after completion of the routing design in each of the layout hierarchies in the general clock routing design method using the above-stated hierarchical layout design. Therefore, it has certain disadvantages as follows:
(1) when a routing design inside each of the layout hierarchies is performed, it is impossible to consider the state of the routing design within another layout hierarchies; PA1 (2) well-balanced routing among the layout hierarchies is unavailable; PA1 (3) it is impossible to perform the clock routing taking a consideration of the whole chip.
In consequence, use of the hierarchy layout design may not only permit a shorter time for the layout design but also impose a less freedom of the routing design. To minimize the clock skew to realize the zero skew routing, it is necessary to repeat the routing design in a trial-and-error fashion, resulting in an increase in the time for the layout design.
In practically proceeding the layout design for LSIs or the like, there are some cases where the layout design of only a part of layout hierarchies goes ahead. In which case, it may happen that the routing process on the clock signal lines is required even if the routing design of all the layout hierarchies is not completed. In the above-mentioned procedure of the general clock routing design, if placement of all layout hierarchies and placement of cells within each of the layout hierarchies are not completed, it is impossible to design the routing of a signal system of, for example, a clock signal branching and extending to each of the hierarchies.